# global variables
# -------------------------
set CHIPNAME mt7688
set TARGETNAME $CHIPNAME.cpu
set ENDIAN little
set CPUID 0x1762824f
# -------------------------


# daemon configuration
# -------------------------
telnet_port 4444
gdb_port 3333

interface sysfsgpio
# -------------------------


# adapter configuration
# -------------------------

# tck tms tdi tdo
sysfsgpio_jtag_nums 12 11 6 1

sysfsgpio_trst_num 0
sysfsgpio_srst_num 3

adapter_nsrst_delay 100
jtag_ntrst_delay 100

reset_config trst_and_srst

# -------------------------


# tap configuration
# -------------------------
jtag newtap $CHIPNAME cpu -irlen 5 -ircapture 0x1 -irmask 0x1f -expected-id $CPUID
# -------------------------


# target configuration
# -------------------------
target create $TARGETNAME mips_m4k -endian $ENDIAN -chain-position $TARGETNAME
#$TARGETNAME configure -work-area-phys 0xa0600000 -work-area-size 0x20000
# -------------------------

# functions configuration
# -------------------------
proc ddrinit { } {
	mem2array romStatus 32 0xB0000028 1
	puts "Ram status is: $romStatus(0)"
	if { [expr $romStatus(0) & 1] == 0 } {
		puts "Rom initalize seems failed, forcing CPU clock from XTAL"
		mem2array CLKCFG0 32 0xB000002c 1
		set CLKCFG0(0) [expr $CLKCFG0(0) | 1]
		array2mem CLKCFG0 32 0xB000002c 1
	} else {
		puts "Rom status OK, ready to initalize CPLL"
		puts "Disable BBPPLL entering SLEEP mode, BBPPLL 480MHz Clock Enable"
		mem2array CLKCFG0 32 0xB000002c 1
		set CLKCFG0(0) [expr $CLKCFG0(0) | 12]
		array2mem CLKCFG0 32 0xB000002c 1
		puts "Initalizing CPLL..."
		mem2array DYNCFG0 32 0xB0000440 1
		set DYNCFG0(0) [expr $DYNCFG0(0) & 4294963440]
		set DYNCFG0(0) [expr $DYNCFG0(0) | 2561]
		array2mem DYNCFG0 32 0xB0000440 1
		mem2array CLKCFG0 32 0xB000002c 1
		set CLKCFG0(0) [expr $CLKCFG0(0) & 4294967280]
		set CLKCFG0(0) [expr $CLKCFG0(0) | 12]
		array2mem CLKCFG0 32 0xB000002c 1
		mem2array CLKCFG0 32 0xB000002c 1
		set CLKCFG0(0) [expr $CLKCFG0(0) | 8]
		array2mem CLKCFG0 32 0xB000002c 1
	}
	puts "Finish initalize CPLL"
	puts "Waiting sometime for DRAM IO PAD initalize"
	sleep 200
	puts "Set DRAM IO PAD for MT7628IC, DDR LDO Enable"
	mem2array RGCTL100 32 0xB0001100 1
	set RGCTL100(0) [expr $RGCTL100(0) | 2147483648]
	array2mem RGCTL100 32 0xB0001100 1
	mem2array RGCTL10C 32 0xB000110C 1
	puts "Set DRAM LDO_1P8V"
	set RGCTL10C(0) [expr $RGCTL10C(0) & 4294967231]
	array2mem RGCTL10C 32 0xB000110C 1
	puts "DDRLDO Soft Start!"
	mem2array RGCTL10C 32 0xB000110C 1
	set RGCTL10C(0) [expr $RGCTL10C(0) | 65536]
	array2mem RGCTL10C 32 0xB000110C 1
	puts "Soft Started, sleeping for some time..."
	sleep 200
	puts "Initalizing PAD..."
	mem2array RGCTL10C 32 0xB000110C 1
	set RGCTL10C(0) [expr $RGCTL10C(0) | 262144]
	array2mem RGCTL10C 32 0xB000110C 1
	mem2array RGCTL104 32 0xB0001104 1
	set RGCTL104(0) [expr $RGCTL104(0) | 1024]
	array2mem RGCTL104 32 0xB0001104 1
	# clean CLK PAD (2
	mem2array RGCLKPAD 32 0xB0001704 1
	set RGCLKPAD(0) [expr $RGCLKPAD(0) & 4294963440]
	# clean CMD PAD (3 
	mem2array RGCMDPAD 32 0xB000170C 1
	set RGCMDPAD(0) [expr $RGCMDPAD(0) & 4294963440]
	# clean DQ IPAD (4
	mem2array RGDQIPAD 32 0xB0001710 1
	set RGDQIPAD(0) [expr $RGDQIPAD(0) & 4294965503]
	# clean DQ OPAD (5
	mem2array RGDQOPAD 32 0xB0001714 1
	set RGDQOPAD(0) [expr $RGDQOPAD(0) & 4294963440]
	# clean DQS IPAD (6
	mem2array RGDQSIPAD 32 0xB0001718 1
	set RGDQSIPAD(0) [expr $RGDQSIPAD(0) & 4294965503]
	# clean DQS OPAD (7
	mem2array RGDQSOPAD 32 0xB000171C 1
	set RGDQSOPAD(0) [expr $RGDQSOPAD(0) & 4294963440]
	# Check chip id
	mem2array CHIPREVID 32 0xB000000C 1
	set CHIPREVID(0) [expr $CHIPREVID(0) >> 16]
	puts "Chip ID: $CHIPREVID(0)"
	if { [expr $CHIPREVID(0) & 1] == 0 } {
		puts "Chip ID found, MT7628_KN"
		set RGCLKPAD(0) [expr $RGCLKPAD(0) | 771]
		set RGCMDPAD(0) [expr $RGCMDPAD(0) | 771]
		set RGDQOPAD(0) [expr $RGDQOPAD(0) | 771]
		set RGDQSOPAD(0) [expr $RGDQSOPAD(0) | 771]
	} else {
		mem2array SYSCFG0 32 0xB0000010 1
		puts "Chip ID found, MT7628_AN"
		if { [expr $SYSCFG0(0) & 1] == 1 } {
			puts "MT7628AN with DDR1 found"
			set RGCLKPAD(0) [expr $RGCLKPAD(0) | 3084]
			set RGCMDPAD(0) [expr $RGCMDPAD(0) | 514]
			set RGDQOPAD(0) [expr $RGDQOPAD(0) | 1799]
			set RGDQSOPAD(0) [expr $RGDQSOPAD(0) | 3084]
		} else {
			puts "MT7628AN with DDR2 found"
			set RGCLKPAD(0) [expr $RGCLKPAD(0) | 3084]
			set RGCMDPAD(0) [expr $RGCMDPAD(0) | 514]
			set RGDQOPAD(0) [expr $RGDQOPAD(0) | 1028]
			set RGDQSOPAD(0) [expr $RGDQSOPAD(0) | 3084]
		}
	}
	# Set PAD Configuration
	puts "Setting PAD register..."
	array2mem RGCLKPAD 32 0xB0001704 1
	array2mem RGCMDPAD 32 0xB000170C 1
	array2mem RGDQIPAD 32 0xB0001710 1
	array2mem RGDQOPAD 32 0xB0001714 1
	array2mem RGDQSIPAD 32 0xB0001718 1
	array2mem RGDQSOPAD 32 0xB000171C 1
	puts "Release DDR RST..."
	mem2array RSTCTL 32 0xB0000034 1
	set RSTCTL(0) [expr $RSTCTL(0) & 4294966271]
	array2mem RSTCTL 32 0xB0000034 1
	puts "Done!"
}

proc load_ramboot { } {
	reset halt
	ddrinit
	load_image ramboot.bin 0x80200000
	resume 0x80200000
}
# -------------------------

# workarea configuration
# -------------------------
mt7688.cpu configure -work-area-phys 0x00000000 -work-area-size 0x0010000  -work-area-backup 0
# -------------------------
